Technology scaledown and frequency increase have brought new standards to integrated circuit manufacturing. Common techniques in circuit design and simulation are gradually becoming less effective. Increased variation in semiconductor devices and interconnect or voltage drops over power supplies due to increased currents and parasitics make delay and power consumption estimation more complicated. See e.g., Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden, “Design and Analysis of Power Distribution Networks in PowerPC Microprocessors”, Proceedings of the 35th Annual Conference on Design Automation, which is incorporated herein by reference in its entirety.
Deterministic models are ineffective in handling new specifications, or they require cumbersome calculations which incur high run-time cost. New techniques have been developed, such as statistical static time analysis (SSTA) and power supply network voltage drop estimation, capable of functioning with modern technology requirements. See e.g., Anirudh Devgan, Chandramouli Kashyap, “Block-based Static Timing Analysis with Uncertainty”, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design or power supply voltage drop estimation; and N. E. Evmorfopoulos, D. P. Karampatzakis, G. I. Stamoulis, “Precise identification of the worst-case voltage drop conditions in power grid verification”, International conference on Computer-aided design 2006, which are each incorporated herein by reference in their entirety.
In SSTA, models do not specify a specific delay for a cell but a time interval is provided along with probabilities. Due to power supply voltage drop, path analysis is no longer effective for estimating path delay. A number of simulations are required to estimate power grid behavior during transitions. Only then, knowing at the specific time the accurate power supply value, accurate delay of the cell be extracted and thereupon path delay.
These and other considerations lead to a quest for novel tools that incorporate new design attributes. These tools can perform analyses based on new models as well as perform statistical estimations based on a large number of simulations. This can include tools that perform electrical level simulation, as SPICE does, but in a much faster way.